The role of the embedded memories in the implementation of artificial neural networks

Abstract

The paper describes the implementation of a systolic array for a multilayer perceptron on different FPGA architectures with a hardware-friendly learning algorithm: Pipelined On-line Backpropagation. By exploiting the embedded memories of certain families alongside the projection used in the systolic architecture, we can implement very large interconnection layers. These physical and architectural features – together with the combination of FPGA reconfiguration properties with a design flow based on generic VHDL – permit us to create an easy, flexible and fast method of designing a complete ANN on a single FPGA. The result offers a high degree of parallelism and fast performance.