Performance Analysis of Devices in Double Gate MOSFET

Abstract

The silicon CMOS technology moves into the sub-20nm regime and due to manufacturing limits the fundamental curb the traditional scaling of transistors. Rapid development in device structures and materials will be need for transistor miniaturization and improvement of performances. Device dimensions are approaching to their scaling limit rise to undesirable effects i.e. drain induced barrier lowering (DIBL), gate leakage current, short channel effects etc. Tri-Material Double Gate (DMDG) structure offers an alternative way of simultaneous SCE suppression and improved device performance by careful control of the gate material work function. We study and analyze the short channel effects (SCE), potential distributions, impact ionization, ion scattering, hot carrier effect and sub threshold swing. Analysis and comparative study of the electrical characteristics of DOUBLE GATE FETs shows that TMDG MOSFET exhibits better performance than DMDG and SMDG MOSFET in terms of surface potential, electric field, carrier mobility, and electron velocity to suppress the scaling effects like DIBL, HCEs etc.