Variance Reduction during the Fabrication of Sub-20 nm Si Cylindrical Nanopillars for Vertical Gate-All-Around Metal-Oxide-Semiconductor Field-Effect Transistors

Abstract

The variance of sub-20 nm devices is a critical issue for large-scale integrated circuits. In this work, uniform sub-20 nm Si nanopillar (NP) arrays with a reduced diameter variance (to ±0.5 nm) and a cylindrical shape, which can be used for vertical gate-all-around metal-oxide-semiconductor field-effect transistors, were fabricated. For the fabrication process, an array of tapered Si NPs with a diameter of approximately 62.7 nm and a diameter variance of ±2.0 nm was initially fabricated by an argon fluoride lithography followed by dry etching. Then, the NPs were oxidized in a self-limiting region. After the oxide removal, a similar oxidation process was used again for the NPs. It is determined that by controlling oxidation in the self-limiting region, the diameter variance can be reduced in the height direction of Si NPs (as well as shape control) and between NPs, simultaneously with a controllable diameter decrease. This approach decreases the variance in size caused by conventional nanoprocessing and helps overcome the position-dependent variance for 300 mm φ wafers, which is caused by current semiconductor processing.