Cross-coupled dynamic CMOS latches: Robustness study of timing

Abstract

This paper presents an in-depth analysis of the propagation delay of dynamic CMOS latches and its variability when subjected to process, voltage and temperature (PVT) variations. Three basic topologies namely the cascade voltage switch logic (CVSL), dynamic single transistor clocked (DSTC) and dynamic ratio insensitive (DRIS) have been investigated for robustness and switching characteristics. The extensive analysis provides well-defined guidelines for selection of variation-aware CMOS latches used in digital logic design. All simulations have been performed on 180 nm TSMC industry standard technology node using SPICE circuit simulator.