Simulation of parasitic interconnect capacitance for present and future ICs

Abstract

The performance of modern integrated circuits is often determined by interconnect wiring requirements. Moreover, continuous scaling of VLSI circuits leads to an increase in the influence of interconnects on system performance. It is desired therefore, to calculate accurately its parasitic components, particularly wiring capacitance. In order to recognize which one from the most popular empirical approaches gives the evaluation of the total capacitance that suits to the real capacitance of the interconnect line, the numerical simulations based on the numerical solving of Maxwell equations have been employed. © Springer-Verlag Berlin Heidelberg 2005.