Three phase dynamic current mode logic: A more secure DyCML to achieve a more balanced power consumption

Abstract

In order to protect cryptographic devices against power analysis attacks, circuit level countermeasures can be used. Using dynamic current mode logic(DyCML) is an efficient countermeasure providing that the routing of dual-rail signals is balanced. In this paper, we have developed a new logic style based on DyCML, which provides side-channel security without the balanced routing requirement. Simulations of 1-bit full adder were performed to compare the proposed logic style with SABL and DyCML in terms of side-channel security. Post layout simulation results show improvement of normalized energy deviation(NED) of 50% and normalized standard deviation(NSD) of 63% compared with DyCML. Finally, for the AES Sbox simulation, our proposed logic style improves by 31% in NED and by 40% in NSD compared to other secure logics.