Analysis of Metastable Operation in a CMOS Dynamic D-Latch

Abstract

Nowadays, metastability is becoming a serious problem in high-performance VLSI design, mainly due to the relatively-high probability of error when a bistable circuit operates at high frequencies. As far as we know, there is not any work published that justifies and formally characterizes metastable behavior in dynamic latches. With current technologies, dynamic latches are widely used in high-performance VLSI circuits, mainly due to their lower cost and higher operation speed than static latches. In this work, we demonstrate that dynamic memory cells present an anomalous behavior referred to as metastable operation with characteristics similar to those of static latches. We perform a suitable generalization of metastability to the dynamic case, applying it to a CMOS dynamic D-latch. A theoretical model will be proposed, allowing the quantification of metastability, and it will be validated through electric simulation with HSPICE. After that, we have compared the metastable behavior of the dynamic latch with its static counterpart, obtaining results about the characteristic parameters of metastability and the Mean Time Between Failures (MTBF) for both kinds of bistable circuits. These results have allowed us to conclude that, unlike metastability windows in static latches, a clearly defined input interval exists which produces an infinite resolution time. Regarding MTBF, the dynamic latch presents a very low MTBF value compared to the static latch. These results show that dynamic latches should not be used in those circuits where the risk of asynchronism between clock and data signals is not negligible.