Reducing cache conflicts by a parametrized memory mapping

Abstract

Algorithms which access memory regularly are typical for scientific computing, image processing and multimedia. Cache conflicts are often responsible for performance degradation, but can be avoided by an adequate placement of data in memory. The huge search space for such compile time placements is systematically reduced until we arrive at a class of very simple mappings, well known from data distribution onto processors in parallel computing. The choice of parameters is then guided by a cost function which reflects the tradeoff between additional instruction overhead and reduced miss penalty. We show by experiment that when keeping the overhead low, a considerable speedup can be achieved.