A routing architecture for FPGAs with dual-VT switch box and logic clusters

Abstract

In this paper, we present a novel routing architecture for FPGAs with dual-V T LUT and switch box architectures. The use of reverse back bias (RBB) is one strategy for mitigating leakage power, a critical issue as process technologies shrink relentlessly towards sub-nano proportions. FPGAs with the ability to adjust fabric V T at configuration time offer leakage power reduction without sacrificing circuit speed. Most of the related works today investigate dual-V T optimizations at the logic cluster level; Altera's Stratix-III/IV line of FPGAs already demonstrate the feasibility of a similar architecture. In this work, we present a further advancement to the dual-V T architecture - the switch box, and a routing architecture that demonstrates the effectiveness of this true dual-V T fabric architecture. Our switch box advancement alone yields an average of 17.44% in leakage power savings, and with the full EDA flow an average 29.65% in total power savings is observed. © 2012 Springer-Verlag.