The Charge Sheet Model Revisited

Abstract

We review in this chapter the main attributes of the ‘Charge Sheet Model’ (C.S.M.) introduced by J.R. Brews in 1978 (Brews 1978; Van de Wiele 1979). Although its name contains the word ‘Model’, the C.S.M is not a design tool. It is an invaluable means however for understanding some of the mechanisms governing current in MOS transistors for it scrutenizes phenomena otherwise difficult to apprehend. Unfortunately, the C.S.M. concerns only long channel MOS transistors implemented in a uniformly doped substrate (gradual channel approximation). Trying to predict drain currents of real transistors with the C.S.M. does not work. Figure 2.1 depicts the structure of the NMOS transistor considered throughout this chapter. The two vertical lines without any other demarcation called respectively S and D symbolize the source and drain junctions. Two-dimensional effects are ignored, obliterating consequently items such as channel length modulation, Drain Induced Barrier Lowering (DIBL), etc. The source, drain and gate voltages are called respectively VS, VD and VG, the surface potential ψS and the non-equilibrium voltage V. The latter, called also the channel voltage, varies from VS at the source to VD at the drain. Single indices relate to voltages defined with respect to the substrate. Double indices relate to voltages defined with respect to references other than the substrate. For instance, VGS is the voltage difference between the gate and the source.