Abstract
This paper describes a parallel architecture for a variety of algorithms for video compression. It has been designed to meet the requirements of encoding and decoding according to the ITU-T standard H.263. The architecture is an implementation of the instruction systolic array (ISA) model which combines the simplicity of systolic arrays with the flexibility of a programmable parallel computer. Although the parallel accelerator unit is implemented on no more than 9 mm2 of silicon it suffices to meet the compression rate necessary to send a compressed video stream through a standard ISDN terminal interface. © Springer-Verlag Berlin Heidelberg 1999.
Cite
CITATION STYLE
Schmidt, B., & Schimmler, M. (1999). A parallel accelerator architecture for multimedia video compression. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 1685 LNCS, pp. 950–960). Springer Verlag. https://doi.org/10.1007/3-540-48311-x_133
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