Abstract
Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. In this paper Reverse Body Bias (RBB) with high-Vth is used to reduce the leakage power in nanometer technology for the proposed array multiplier with CSA design. The results are carried out by H-Spice for 90nm and 65nm BSIM model files. MTCMOS circuits have shown good results than the conventional circuits. © 2012 Springer-Verlag.
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Nirlakalla, R., Boothuru, B. R., Thota, S. R., Rajasekhar Babu, M., Talari, J. P., & Venkata Krishna, P. (2012). Designing of power optimized bypassing array multiplier in nanometer technology. In Communications in Computer and Information Science (Vol. 270 CCIS, pp. 277–284). https://doi.org/10.1007/978-3-642-29216-3_30
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