This chapter presents a 480 MHz, continuous time, 6th order band-pass Sigma Delta Analog to Digital modulator in IBM 0.18 um CMOS technology. We replace traditional RLC circuits, containing spiral inductors with high quality factor, active inductor based resonators utilizing negative impedance circuits. This reduces chip area and eliminates post processing needs. Pad to pad simulation of the extracted layout in Cadence yields an enhanced SNDR of 70 dB and power consumption of 29 mW. The modulator occupies 0.5 mm2 of chip area. © 2014 Springer Science+Business Media Dordrecht.
CITATION STYLE
Dobson, K., Ahmadi, S., & Zaghloul, M. (2014). A 480 MHz band-pass sigma delta analog to digital modulator with active inductor based resonators. In Lecture Notes in Electrical Engineering (Vol. 247 LNEE, pp. 1–11). Springer Verlag. https://doi.org/10.1007/978-94-007-6818-5_1
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