Design of new tester circuit for fault detection

Abstract

Fault detection plays an important role in detecting faults and helps to reduces the yield loss in manufacturing process of ICs. Due to the smaller size and process variations, IC chips become more sensitive. Thus there is thriving necessity for fault tolerance which can be obtained by an efficient fault detection concept. In this paper, new tester circuit is designed for fault detection using different tester circuits that are existed. This design has been simulated in 180nm, 65nm CMOS technology using cadence Virtuoso tool. By using transmission gates instead of pass transistors the modified circuit provides full swing voltage at output.