Time-interleaved Track and Holds

Abstract

Chapter 2 describes the Track and Hold (T&H) architecture for a time-interleaved ADC. Mismatch between channels, like difference in offset, gain and timing, degrades the performance and therefore this topic is investigated in detail. Two T&H architectures are discussed, one with a frontend sampler and one without. The use of a frontend sampler has the advantage of good timing alignment between channels, the resistance of the switch is however a problem: it limits both the input bandwidth and the achievable resolution and the track-time has to be less than one sample period. A new open-loop buffer is introduced together with a new technique to increase its bandwidth. The result of this combination is a T&H buffer with good linearity and high bandwidth, while the power consumption is kept low. The topic of calibration is discussed and while offset and gain calibrations are relatively easy to implement, timing calibration is much harder to realize: it requires high-frequency test-signals and the required adjustable timing circuitry causes jitter by itself.