Smart Multicrossbar Router Design in NOC

Abstract

This paper gives the innovative idea of designing a router using multicrossbar switch in Network on Chip(NoC). In Network-on-Chip architectures the input buffer can consume a large portion of the total power. Eliminating all input buffer would result in increased power consumption at high load, while reducing the size of input buffer degrades the performance. In this paper we have proposed a muticrossbar router design using elastic buffer by combining the advantage of both buffered and buffer less network. In the proposed design Power Delay Product is reduced by around 37 .91% as compared to baseline router.