Leakage power reduction technique by using finFET technology in ULSI circuit design

Abstract

Deep Sub Micron (DSM) technology demands for lower supply voltage, reduced threshold voltage and high transistor density which leads to exponentially increase in leakage power when circuit is in standby mode. Here review of FinFET transistor along with existing low power techniques in DSM circuits like sleep, LECTOR etc. are done. Then Lector with FinFET technology circuit is proposed. This work evaluates the impact of FinFET technology, which has huge potential to replace bulk CMOS in DSM range. Performance of proposed technique is investigated in terms of dynamic power, delay, Power Delay Product (PDP) and leakage power dissipation. The proposed techniques has leakage controlling sleep transistor inserted over pull up and pull down network which significantly reducing the leakage power by using HSPICE simulator in 32 nm FinFET technology at 25 and 110 °C with CL = 1 pF at 100 MHz frequency.