Analyzing the hardware costs of different security-layer variants for a low-cost RFID tag

Abstract

Radio-frequency identification (RFID) technology is the enabler for the future Internet of Things (IoT) where security will play an important role. In this work, we evaluate the costs of adding different security-layer variants that are based on symmetric cryptography to a low-cost RFID tag. In contrast to related work, we do not only consider the costs of the cryptographic-algorithm implementation, but also the costs that relate to protocol handling of the security layer. Further we show that using a tag architecture based on a low-resource 8-bit microcontroller is highly advantageous. Such an approach is not only flexibility but also allows combining the implementation of protocol and cryptographic algorithm on the microcontroller. Expensive resources like memory can be easily reused, lowering the overall hardware costs. We have synthesized the security-enabled tag for a 130 nm CMOS technology, using the cryptographic algorithms AES and NOEKEON to demonstrate the effectiveness of our approach. Average power consumption of the microcontroller is 2 μ W at a clock frequency of 106 kHz. Hardware costs of the security-layer variants range from about 1100 GEs using NOEKEON to 4500 GEs using AES. © 2012 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering.