The power-efficient implementation of motion estimation algorithms on a system comprised by an FPGA and an external memory is presented. Low power consumption is achieved by implementing an optimum on-chip memory hierarchy inside the FPGA, and moving the bulk of required memory transfers from the internal memory hierarchy instead of the external memory. Comparisons among implementations with and without this optimization, prove that great power efficiency is achieved while satisfying performance constraints. © Springer-Verlag Berlin Heidelberg 2003.
CITATION STYLE
Tatas, K., Siozios, K., Soudris, D., & Thanailakis, A. (2003). Power-efficient implementations of multimedia applications on reconfigurable platforms. Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2778, 1032–1035. https://doi.org/10.1007/978-3-540-45234-8_113
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