Design of a power efficient ALU using reversible logic gates

Abstract

Today’s VLSI design technology is moving very quickly into low power, high speed and micro areas of development. Reversible logic has played an important role in this, notably in quantum computing and DNA computing, and presently moving into optical computing also. It is also found that under some ideal conditions it can produce zero power dissipation. A known fact that an arithmetic logic unit (ALU) is one of the core components of a the CPU in a computer. The design of an ALU using different reversible logic gates is proposed. The proposed reversible logic-based ALU is implemented using a Mentor Graphics tool in 130 nm technology for power efficiency. The power dissipation of two proposed ALU designs and a conventional area-based ALU have been compared. The conventional ALU dissipates the power 10% reversible logic-based ALU.