High-voltage IC technology: Implemented in a standard submicron CMOS process

Abstract

This paper describes a high-voltage IC technology. Various novel lateral high-voltage device concepts, which can be efficiently implemented in a submicron CMOS process, are explained and analyzed. It’s essential for lateral high-voltage devices to show best trade-off between specific on-resistance Rsp and breakdown voltage BV, and super-junction devices give an opportunity to achieve a best Rsp-BV trade-off for BV over 100V. Key issues for monolithic integration of high-voltage devices and low-voltage CMOS are reviewed in the paper. Finally, hot-carrier (HC) behaviour of a high-voltage 0.35μm lateral DMOS transistor (LDMOSFET) is presented. It is shown that self-heating effects during HC stress have to be taken into account for the HC stress analysis. Together with TCAD simulations and measurements, one can clearly explain the self-heating effects on the HC behaviour of an LDMOSFET.