System architecture directions for post-SoC/32-bit networked sensors

N/ACitations
Citations of this article
55Readers
Mendeley users who have this article in their library.

Abstract

The emergence of low-power 32-bit Systems-on-Chip (SoCs), which integrate a 32-bit MCU, radio, and flash, presents an opportunity to re-examine design points and trade-offs at all levels of the system architecture of networked sensors. To this end, we develop a post-SoC/32-bit design point called Hamilton, showing that using integrated components enables a ∼$7 core and shifts hardware modularity to design time. We study the interaction between hardware and embedded operating systems, identifying that (1) post-SoC motes provide lower idle current (5.9 µA) than traditional 16-bit motes, (2) 32-bit MCUs are a major energy consumer (e.g., tick increases idle current >50 times), comparable to radios, and (3) thread-based concurrency is viable, requiring only 8.3 µs of context switch time. We design a system architecture, based on a tickless multithreading operating system, with cooperative/adaptive clocking, advanced sensor abstraction, and preemptive packet processing. Its efficient MCU control improves concurrency with ∼30% less energy consumption. Together, these developments set the system architecture for networked sensors in a new direction.

Cite

CITATION STYLE

APA

Kim, H. S., Andersen, M. P., Chen, K., Kumar, S., Zhao, W. J., Ma, K., & Culler, D. E. (2018). System architecture directions for post-SoC/32-bit networked sensors. In SenSys 2018 - Proceedings of the 16th Conference on Embedded Networked Sensor Systems (pp. 264–277). Association for Computing Machinery, Inc. https://doi.org/10.1145/3274783.3274839

Register to see more suggestions

Mendeley helps you to discover research relevant for your work.

Already have an account?

Save time finding and organizing research with Mendeley

Sign up for free