AESOP: A TOOL FOR AUTOMATED TRANSISTOR SIZING.

Abstract

The problem of automating the electrical optimization of combinatorial MOS circuits is addressed. Linear algorithms are presented for computing optimal transistor sizes to minimize delay, area or power consumption. This optimization as well as an increase in speed is sought without changing the circuit's structure, number of gates or clocking. These algorithms are implemented in the interactive tool, Aesop. When compared to manual designs, the circuits produced by Aesop are typically faster or have substantially lower area and power consumption. Compared to untuned circuits, Aesop typically increases circuit speed by a factor of 2 to 4. Alternatively, power consumption and transistor area can be reduced by 25-50% with no sacrifice in circuit speed. These improvements are computed interactively on a professional workstation for circuits containing thousands of transistors.