A Fine-Grained power gating technique for reducing the power consumption of embedded processor

Abstract

In the deep submicron process, the power leakage has become the major part of power consumption in the embedded processor. This paper proposes a technique of fine-grained power gating by dynamically and timely turning on or turning off the power supply for functional components in advance. Full use of the structure of the pipeline may eliminate the delay caused by power gating. On the basis of analyzing and using the results of decode unit as the power gating signal, this technique can predict the execution of functional component in two cycles; thus the delay caused by power gating can be eliminated, while the power leakage of embedded processors can be reduced. Experiments show that the technique can reduce 48 % dynamic power consumption and 39 % leakage power consumption of LEON3 processor under the condition of no performance loss.