Accelerating Boolean Satisfiability on an FPGA

Abstract

Boolean satisfiability ({SAT}) is a core {NP}-complete problem. Several heuristic software and hardware approaches have been proposed to solve this problem. In this work, we present a hardware solution to the {SAT} problem.We propose a custom {IC} to implement our approach, in which the traversal of the implication graph as well as conflict clause generation is performed in hardware, in parallel.