Pulsed-laser-induced epitaxial growth of silicon for three-dimensional integrated circuits

Abstract

Pulsed-Laser-induced epitaxial growth (PLEG) is an attractive method for lateral overgrowth of orientation-controlled silicon (Si). As underlying MOSFETs on the seeding crystalline Si wafer is not thermally damaged, the PLEG is promising for monolithic 3D integration of circuits. This paper will review our systematic studies of both simulation and experiment on the PLEG of Si aimed for fundamental understanding of the epitaxial growth and reduction of defect generation. Experimentally a XeCl excimer-laser irradiates the sample which consists of amorphous-silicon (a-Si) deposited on a thick SiO2 with a small contact opening on a _100_ oriented SOI or bulk-Si wafer. The experiment verified our 2D transient heat transfer simulation results that the combination of the long-pulse and the bulk- Si wafer gives the widest process window. The bulk-Si wafer seeding provided the larger Si island size of 6 μm than that of the SOI (4 μm). From Electron Backscattering Diffraction (EBSD) analysis it was found that _100_ is the main surface crystallographic orientation. However there exist four, isolated secondary sub-grains inside the Si island. TEM cross-sectional image revealed formation of the subgrains due to formation of Σ3 (111) type of coincident site lattice (CSL) boundary originated at the SiO2 sidewall. We believe that the gentle slope of the side wall allows the extension of the facet to the CSL boundary and subgrains. At last we introduced a way to reduce the CSL boundary formation in the PLEG of Si. By using 75◦ steep sidewalls of the opening to the seed, we have successfully obtained an array of Si islands having a size of 4 μm with {100} surface orientation only, without any subgrains inside.