Green experiments with FPGA

Abstract

The opportunity of the modern CAD and feature of FPGA for development of the power-efficient digital components of computer systems are examined experimentally. Possibilities of a preliminary estimate of energy consumption in the project implemented in Altera FPGA are analyzed. The possibility of an assessment of energy consumption distribution between parts of the project circuit by control of signals activity is shown. Influence of the partial failure of circuits of the general signals on energy consumption of the FPGA circuit is researched. The possibility of monitoring of the general signals in the circuit according to its energy consumption is shown. A problem of the glitches caused by signal races with parasitic transitions leading to essential power losses is considered. The program model developed for an assessment of glitches in the iterative array multiplier shows repeated exceeding of number of parasitic transitions in comparison with the number of functional ones. The matrix parallelism which is widely used in the FPGA circuits is the cornerstone of the problem of glitches. Experiments with FPGA show solution this problem by simplification of array structures in use of additional and natural pipelining and in execution of the truncated operations.