Stochastic local search methods such as GSAT, WalkSAT and their variants have been used successfully at solving propositional satisfiability problems (SAT). The key operation in these local search algorithms is the speed of variable flipping. We present a parallel FPGA designs for CSAT capable of one flip per clock cycle which is achieved by exploiting maximal parallelism and "multi-try" pipelining. Experimental results show that a speedup of two orders of magnitude over software implementations can be achieved. © Springer-Verlag Berlin Heidelberg 2002.
CITATION STYLE
Henz, M., Tan, E., & Yap, R. H. C. (2002). Implementing CSAT local search on FPGAs. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 2438 LNCS, pp. 1156–1159). Springer Verlag. https://doi.org/10.1007/3-540-46117-5_130
Mendeley helps you to discover research relevant for your work.