High-level partitioning of digital systems based on dynamically reconfigurable devices

Abstract

This paper presents a high-level temporal partitioning algorithm, which is able to split the VHDL description of a digital system into two equivalent subdescriptions. The primary goal of the algorithm is to obtain two area-balanced, time-independent partitions. The descriptions of these partitions can be separately simulated, synthesized and implemented as different configurations of a dynamically reconfigurable device. The partitioning principle is based on a directed task hypergraph. Each vertex of this hypergraph corresponds to one concurrent assignment of the description being analysed. The resources required for the physical implementation of each vertex are calculated by means of a simplified resource estimator. Time dependencies between vertices are denoted by hyperedges representing signals connecting appropriate concurrent assignments. © Springer-Verlag Berlin Heidelberg 2002.