Design for manufacture in overlay metrology

Abstract

Overlay metrology has become a cornerstone requirement which enables modern lithographic patterning. The mantra of metrology engineers in the litho cell and tool vendors alike has traditionally been TMU - Total Measurement Uncertainty - a metric which combines all sources of metrology tool related uncertainty. Although relentless TMU reduction is essential, it is certainly not a sufficient condition to meet the overlay control needs for the 32 nm node and below. Many other "on wafer" contributors must be factored into the uncertainty equation. A wider scope in the definition of the overlay metrology process is required which views it as part of the greater IC manufacturing process. Current and emerging overlay metrology industry practices will be reviewed in light of the increasing complexity associated with the interactions between metrology tool, target design and the sampling plan. © 2005 American Institute of Physics.