Design of a 16 bit RISC processor

Abstract

Objectives: This paper presents the design of a 16 bit Reduced Instruction Set Computing (RISC) processor using the custom design approach. Statistical Analysis: The type of processor employed in a system claims its efficiency. The compressed instruction incorporated in the design reduces the area and power dissipation of the processor. Findings: Various functional blocks of the processor such as the Control Unit, Instruction Decoder, Instruction Register unit and Arithmetic and Logical Unit (ALU) are designed using the Cadence® Virtuoso tool and the simulations are carried out using Cadence® ADE_L Tool using 180nm technology library from TSMC. The integration of the various functional bocks is done based on the finite states arrived at, for the execution of each instruction. Conclusion: The RISC processor is found to consume 68.9mW of power for the execution of the AND instruction with a delay of 1600ns. It consumes 77.6mW of power dissipation for the execution of the ADD instruction with a delay of 1900ns.