A neuromorphic majority function circuit with o(N) area complexity in 180 nm CMOS

Abstract

An artificial neuron with a step activation function is first designed and verified. Thereafter, a synaptic weight generation circuitry is designed to provide a suitable sum current to the activation function neuron to achieve the task of majority function generation for digital logic inputs. HSPICE simulations are performed to verify the proposed theoretical framework, with the proposed network correctly yielding the appropriate low or high digital logic state corresponding to the input combinations applied. Superiority of the proposed circuit in terms of transistor area required is also demonstrated. The transistor count increase linearly with the number of variables in the case of the proposed circuit; whereas for conventional static CMOS implementations an exponential increase in transistor count is exhibited.