Hybrid digit-serial multiplier for shifted polynomial basis of GF(2m)

Abstract

Recently, a shifted polynomial basis is a variation of polynomial basis representation. Such kind basis provides better performance in designing bit-parallel and subquadratic space complexity multipliers over binary extension fields. In this paper, we study a new shifted polynomial basis multiplication algorithm to implement a hybrid digit-serial multiplier. The proposed algorithm effectively integrates classic schoolbook multiplication, Karatsuba multiplication algorithms to reduce computational complexity, and the modular multiplication with the shifted polynomial basis reduction. We note that, comparably, the proposed architecture achieves lower computation time and higher bit-throughput compared to the best known digit-serial multipliers. Our proposed multipliers can be modular, regular, and suitable for very-large-scale integration (VLSI) implementations. The proposed digit-serial architecture makes the hardware implementations of cryptographic systems more high-performance, and are thus much suitable for efficient applications such as the elliptic curve cryptography (ECC) and pairing computation.