Hardware to solve sparse systems of linear equations over GF(2)

Abstract

Bernstein [1] and Lenstra et al. [5] have proposed specialized hardware devices for speeding up the linear algebra step of the number field sieve. A key issue in the design of these devices is the question whether the required hardware fits onto a single wafer when dealing with cryprographically relevant parameters. We describe a modification of these devices which distributes the technologically challenging single wafer design onto separate parts (chips) where the inter-chip wiring is comparatively simple. A preliminary analysis of a 'distributed variant of the proposal in [5]' suggests that the linear algebra step for 1024-bit numbers could be doable on a 23 × 23-network with special purpose processors in less than 19 hours at a clocking rate of 200 MHz, where each processor has about the size of a Pentium Northwood. Allowing for a 16 × 16 mesh of processing units with 36 mm × 36 mm, the linear algebra step might take less than 3 hours. © Springer-Verlag Berlin Heidelberg 2003.