One of the key metrics to benchmark different 3D architectures is the storage density, which is here indicated with Bit_Density. Given a specific Flash memory die, this density is defined as the ratio between the storage capacity of the die, Die_Capacity, and its silicon area, Die_Size. In this chapter we present some of the most advanced architectures of 3D arrays with vertical channels, which were mainly developed to increase Bit_Density and reduce the Source Line effect.
CITATION STYLE
Crippa, L., & Micheloni, R. (2016). Advanced architectures for 3D NAND flash memories with vertical channel. In 3D Flash Memories (pp. 167–195). Springer Netherlands. https://doi.org/10.1007/978-94-017-7512-0_6
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