An FPGA-Based Architecture for the Versatile Video Coding Multiple Transform Selection Core

Abstract

Versatile video coding (VVC) will be released by 2020, and it is expected to be the next-generation video coding standard. One of its enhancements is multiple transform selection (MTS) for core transform. MTS uses three different types of 2D discrete sine/cosine transforms (DCT-II, DCT-VIII and DST-VII) and up to 64× 64 transform unit sizes. With this schema, significant enhancements of the compression ratio are obtained at the expense of more computational complexity on both encoders and decoders. In this paper, a deeply pipelined high-performance architecture is proposed that implements the three transforms for sizes from 4× 4 to 64× 64 according to working draft 4 of the standard. The design has been described in very high-speed integrated circuit hardware description language (VHDL), and it has been prototyped in a system on a programmable chip (SoPC). It is able to process up to 64 fps@ 3840× 2.160 for 4× 4 transform sizes. To the best of our knowledge, this is the first implementation of an architecture for VVC MTS supporting the 64× 64 size.