Science and Technology of High-Dielectric Constant (K) Thin Films for Next Generation CMOS

Abstract

The microelectronic revolution of the 20*^ Century has been based on silicon because of its exceptional electrical properties and an innate superior insulator, Si02, which enabled the integrated circuit (IC) technology for the microchip. Complementary metal-oxide semiconductor (CMOS) devices, the cornerstone of the Si-IC technology, have been continuously scaled down in the march towards nanoscale logic devices, to achieve faster, cheaper, energy efficient microelectronic systems, and to form the bases for FLASH, DRAM, and EEPROM memories that sustain the current multibillion-dollar memory market. However, the new generation of Si-based nanoscale CMOS devices will clearly need novel paradigms in materials, materials integration, processing, and device architecture beyond the pure Si-based current technology. The technology roadmap^ for the next generation of complementary metal-oxide semiconductor (CMOS) devices indicates that an equivalent oxide thickness (EOT) of less than 1.0 nm is needed to satisfy the requirement of maintaining a suitable capacitance when the gate length, and thus the area (A) of the CMOS gate, is reduced below 65 nm, as shown by the simple parallel plate capacitor equation C = sA/t, where /=thickness of the gate dielectric layer and s the relative permittivity of the dielectric. As the gate length (area) is scaled, the leakage current though the CMOS gate dielectric will be too high when the physical thickness of the Si02 or