A high performance low power 12-bit 40MS/s pipelined ADC

Abstract

A 1.8 V 12-bit 40MS/s pipelined ADC fabricated in a 0.18 μm CMOS process is presented. The traditional closed-loop high performance residue amplifier in first stage is replaced by a simple open-loop amplifier to reduce power dissipation and increase circuit speed in the paper. To improve the stability and response speed of the amplifier, a novel circuit topology of open-loop amplifier is presented in this study. Also, a proposed (1 + 1)-bit/stage structure for pipelined ADC is used in the paper to convert residue voltage that exceeds the convert range. The occupied silicon area is 3.2 × 3.7 mm 2 and the power consumption equals 210mW.