Parallel implementation of A5/2 algorithm

Abstract

A high-speed parallel implementation method of A5/2 algorithm is proposed by improving the conventional architecture in this paper. The operating parallel design of A5/2 algorithm is exploited in initialization, clock controlling stream generation, clock controlled stream generation and key stream generation to enhance the operating speed and the throughput rate of key stream with no increasing of complication in circuit and no decline of the clock frequency nearly. As to the different high-speed methods, this paper performs detailed comparison and analysis. The design has been realized using Altera's FPGA. Synthesis, placement and routing of this parallel design have accomplished on 0.18μm CMOS process. The result proves the critical throughput rate can achieve 1.06Gbps. © 2009 Springer Berlin Heidelberg.