High-performance data processing over N-ary trees

Abstract

An N-ary tree (N≥2) is a connected graph that does not contain cycles and has up to N children for any node. It can be used efficiently to represent data in well-structured hierarchical clusters and to process the data through the parent-child relationships. Several branches of a tree can be handled concurrently, the data hierarchy is described explicitly, and recursion can easily be applied. Thus this model is very appropriate for parallel high-performance computations in areas such as data processing (e.g. sort and search), priority queue management, combinatorial searches and so forth. N-ary trees have been profoundly studied (primarily for N=2) and are supported by software libraries. FPGAs have large embedded dual-port memories with programmable data width for different ports, advanced logic capabilities, and a large potential for parallelism and these features enable N-ary trees with data operations associated with their nodes to be represented more compactly and processed more efficiently in FPGAs than in software. A number of recent research efforts are dedicated to high-performance computations in electronic circuits and systems without the direct use of processing elements, which undoubtedly introduce many constraints (e.g. pre-defined operand sizes, fixed instruction sets, limited concurrency and parallelism). This chapter presents recent advances in this area and is composed of four basic parts: (1) an overview of N-ary trees, their applications, and potential varieties; (2) a discussion of common techniques for implementing and processing N-ary trees in hardware, including their representation in memory, models of computations and algorithms; (3) a description of hierarchical finite-state machines (HFSMs) with extended capabilities (with datapath, in particular) that enable N-ary trees to be processed in hardware and provide support for parallelism, hierarchy and recursion; (4) examples, practical applications, experiments and comparisons of HFSMs. The last part shows that the circuits that have been implemented are faster than the alternatives, and this conclusion is confirmed by examples and experiments in several application areas.