A technique to generate CMOS VLSI flip-flops based on differential latches

Abstract

In this comunication, a new technique to generate flip-flops based on differential structures is presented. This technique is based on the modification of size in transistors of existing differential latches. The limitations of the differential structures to apply this technique are few, so the range of application is high. The main application field is in mixed-signal analog-digital circuits, due to the low switching noise generated by these flip-flops. In this parameter, the behavior is similar in both the proposed flip-flop and the original structure, and better than existing flip-flops.