Fault tolerant and energy efficient signal processing on FPGA using evolutionary techniques

Abstract

In this paper, an energy efficient approach using field-programmable gate array (FPGA) partial dynamic reconfiguration (PDR) is presented to realize autonomous fault recovery in mission-critical (space/defence) signal processing applications at runtime. A genetic algorithm (GA) based on adaptive search space pruning is implemented, for reducing repair time thus increasing availability. The proposed method utilizes dynamic fitness function evaluation, which reduces the test patterns for fitness evaluation. Hence, the scalability issue and large recovery time associated with refurbishment of larger circuits is addressed and improved. Experiments with case study circuits, prove successful repair in minimum number of generations, when compared to conventional GA. In addition, an autonomous self-healing system for FPGA based signal processing system is proposed using the presented pruning based GA for intrinsic evolution with the goal of reduced power consumption and faster recovery time.