Implementation efficiency of BLAKE2 cryptographic algorithm in contemporary popular-grade FPGA devices

Abstract

This paper explores hardware implementations of BLAKE2 cryptographic hash function in the newest popular-grade Spartan-7 device from Xilinx. Specifically, it discusses a particular modification in organization of the cipher hardware eliminating the involved data paths for distribution of message bits among round units – which is accomplished by application of block memory modules for repetitive storage of the message inside each round instance. The idea was applied in four different organizations of the algorithm: the typical iterative one and three high-speed loop-unrolled architectures with 2, 4 and 5 rounds instantiated in hardware. Together with standard (without RAM) implementations this produced a set of 8 test cases: the implementation results allowed to evaluate the proposed modification which, like in our previous studies which used older device families, led to outstanding reductions in FPGA array utilization and also to some improvements in performance parameters.