Abstract
We describe the design by abstract interpretation of a static analysis for the popular hardware language VHDL. From a VHDL description, the analysis computes a superset of the states reachable during any simulation run. This information is useful in the validation of safety properties of hardware components. The construction of the analysis is based on the formal definition of a semantics for VHDL. Soundness with respect to this semantics is shown. Various techniques allow a compromise between the desired accuracy and the cost of the final algorithm. We present a few examples and detail the essential implementation choices. © Springer-Verlag Berlin Heidelberg 2003.
Cite
CITATION STYLE
Hymans, C. (2003). Design and implementation of an abstract interpreter for VHDL. Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2860, 263–269. https://doi.org/10.1007/978-3-540-39724-3_23
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