Data-retention sleep transistor CNTFET SRAM cell design at 32nm technology for low-leakage

Abstract

In today's VLSI Circuits design, one of the key challenges is the increase in power dissipation of the circuits, which in turn shortens the service time of battery-powered electronics, reduces the long-term reliability of circuits due to temperature-induced accelerated device and interconnects aging processes, and increases the cooling and packaging costs of these circuits. Leakage power accounts for an increasingly larger portion of total power consumption in nanometer technologies. A CNTFET is the analogue of silicon MOSFET in which CNTs replace the silicon channel. This paper proposes a new circuit level technique called Data-Retention Sleep transistor method to reduce the standby leakage current in the CNTFET SRAM Cell Design. This technique reduces leakage power by significant amount compared to sleep transistor method with minimal area and delay overhead. © 2013 Springer-Verlag.