Abstract
As modern microprocessros and embedded processors employ deeper pipelines and issue multiple instructions per cycle, accurate branch predictors become an essential part of processor architectures. In this paper, we introduce a history length adjustable gshare predictor for the high-performance embedded processors and show its low-level implementation. Compared to the previous gshare predictor, history length adjustable gshare predictor selectively utilizes the branch history, resulting in substantial improvement in branch prediction accuracy. © Springer-Verlag Berlin Heidelberg 2006.
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CITATION STYLE
Kwak, J. W., Jhang, S. T., & Jhon, C. S. (2006). History length adjustable gshare predictor for high-performance embedded processor. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 3983 LNCS, pp. 631–638). Springer Verlag. https://doi.org/10.1007/11751632_69
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