Analytical delay model for CPU-FPGA data paths in programmable system-on-chip FPGA

Abstract

The CPU hard cores in programmable System-on-Chips (SoC) often communicate with the soft IP cores in reconfigurable fabric through some dedicated ports. The various data paths corresponding to different ports have different performance characterizations which make them suitable for various applications. This article studies the analytical performance model for transferring data stored in CPU side to FPGA side and vice versa through all different communication ports and data paths available in a typical programmable SoC. The proposed methodology for extracting the cycle accurate delay models is applicable to other similar programmable SoCs. Evaluation experiments identified that the error rate of proposed models are within an acceptable rate of 5%.