Improved SQRT architecture for carry select adder using modified common boolean logic

Abstract

The binary adders are the most essential and fundamental circuit element to perform the arithmetic operations in digital computers. These binary adder circuits are widely used in integrated circuits (IC) such as processors, and their usage does not limit inside arithmetic logic unit (ALU) of a processor. In fact these binary adders are also playing key role in various applications like digital filters, digital transformation cores, signal processing elements, digital modulators and demodulators, digital image/video processing, and cryptographic applications. The small performance metric of the binary adder circuit will yield significant advantage in larger computations. Designing of faster, smaller, and more powerful efficient binary adder has been the ultimate challenge for many researchers. To succeed in this challenge, numerous architectures were proposed in past, which results in various architectures for the binary adder. In recent times, the carry select adder (CSLA) architecture was considered as one of the best suitable architectures which showed better performance among the others. Several new architectures were introduced in CSLA to improve its performance further. The area occupied by the CSLA adder is one of the performance metrics to evaluate the efficiency of the CSLA adder. This is because the CSLA adder uses two ripple carry adders for the both states of single carry input. Thus, the adders use two times more circuit elements than necessary. Several approaches like binary-to-excess-1 converter (BEC-1), common boolean logic (CBL), and SQRT architectures were proposed to reduce the area of the CSLA architecture. This article introduced a new approach in SQRT–CSLA adder using modified CBL. The common Boolean logic performs the evaluation of carry-based selection with less area than other design techniques. The design proposed in this article introduced a new CBL architecture which succeeded in reduction of area compared to the previous architectures. The CSLA adders with the proposed CBL architecture were implemented for the various word sizes like 8-bit, 16-bit, and 32-bit. The reduction of area has been clearly observed in the results. These results prove that the proposed CSLA scheme exhibits better performance than the regular SQRT–CSLA.