Leakage current analysis of 6t & 7T-SRAM using finfets at 22nm technology

Abstract

Persistent scaling of planar MOSFET results in increase in transistor package density and performance of chip. However at nanometer regime, it has become a very challenging issue due to the increase in the short channel effects. In nano-scaled MOSFETs, the channel loses control from gate terminal due to potential at drain. Due to this, it is difficult to turn off MOSFET completely which inturn leads to leakage currents. Since cache memory occupies more area of processors, it is difficult to reduce leakage power in microprocessors. Double gate transistors have become replacement for MOS transistors at nano level. Since FINFETs have double gates, the leakage currents can be controlled effectively than planar MOSFET. In this paper, leakage currents of 6T & 7T-SRAM memory cell are analyzed using FINFETs at 22nm technology in hspice software.