SRAM Cell Stability: Definition, Modeling and Testing

Abstract

Modern SRAMs strive to increase bit counts while maintaining low power consumption and high performance. These objectives require continuous scaling of CMOS transistors. The supply voltage mustscale down accordingly to control the power consumption and maintain the device reliability. Scaling the supply voltage and minimum transistor dimensions that are used in SRAM cells challenge the process and design engineers to achieve reliable data storage in SRAM arrays. This task is particularly difficult in large SRAM arrays that can contain millions of bits [23]. Random fluctuations in the number and location of the dopant atoms in the channel induce large threshold voltage fluctuations in scaled-down transistors [41]. Other factors affecting the repeatability of the threshold voltage and introducing VTH mismatches even between the neighboring transistors in SRAM cells are the line edge roughness, the variations of the poly critical dimensions and the short channel effects [42]. SRAM stability margin or the Static Noise Margin (SNM) is projected to reduce by 4X as scaling progresses from 250 nm CMOS technology down to 50 nm technology [41, 43]. Since the stability of SRAM cells is reducing with the technology scaling, accurate estimation of SRAM data storage stability in pre-silicon design stage and verification of SRAM stability in the post-silicon testing stage are increasingly important steps in SRAM design and test flows. This chapter will compare the static and dynamic noise margin (Section 3.2) followed by the discussion of the existing definitions of SRAM SNM (Section 3.3). Analytical expressions for calculating of the SNM of a 6T SRAM cell, the 4T cell with a resistive load and the loadless 4T SRAM cell are described in Section 3.4. The sensitivity study of the SNM to the fabrication process variations, non-catastrophic defect resistance and operating voltage is presented in Section 3.5. In Sections 3.6 and 3.7 we introduce the fault model developed to represent an SRAM cell with a reduced SNM value and the stability detection concept, respectively. The stability detection concept illustrates the principle behind the stability test techniques that we will discuss in detail in Chapter 5. We evaluated the capabilities of several march patterns to detect the stability faults in SRAM cells. The results of this study are discussed in Section 3.8.